Hi All, I am Looking for Senior SOC Verification Engineers for Bangalore &amp; Hyderabad Location. Exp - 10+ yrsLocation - BLR &amp; HYDClients - ProductsNotice Period - Immediate to 30 days Max JD:Design Verification , Asic VerificationSoc VerificationDDR, Pcie, EthernetSystem Verilog, UVM<p

Hi All, Currently i am hiring for Memory Layout Engineers for Bangalore &amp; Hyderabad Location. Experience : 4 to 10TSMC : RequiredInterview Mode : F2F <ul><li>Both Memory/Analog is required but mostly memory&nbsp;background is preferred</li><li>DRAM memory(decoders will be helpful).</li></ul><br

Company OverviewModernize Chip Solutions Pvt. Ltd. is a leading semiconductor services provider offering end-to-end solutions to the global semiconductor industry. Known for our cutting-edge services in ASIC Design, Verification, Physical Design, DFT, Circuit Design &amp; Layout, and FPGA Design and Emulation, we are headquartered in Hyderabad, Telangana, and have a stro

Description: - Accountable for innovative DFT implementation(Scan, MBIST, LBIST &amp; Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. - Generate and validate ATPG patterns using simulations. - Shall Validate the DFT implementation using RTL and Gate level simulation. - Work

PD methodology and library validation Role: The individual would work in Design Enablement team for Physical Design flow and library validation.This includes RTL to GDS2 integration validation of test blocks implemented with different std cell architectures, macros and across different technologies.Sign-off flow validation like STA, DRC, LVS, PEX will be part of t

Company OverviewModernize Chip Solutions Pvt. Ltd. is a rapidly growing company in the semiconductor services sector, offering high-quality, swift end-to-end solutions. Specializing in ASIC design, verification, physical design, and more, the company caters to the global semiconductor industry. With headquarters in Hyderabad, Telangana, and a workforce of 200-500 employe

Modernize chip solutions is one of the fastest-growing semiconductor services company. We deliver end-to-end solutions of the best quality with the shortest development cycle to the global semiconductor industry. Our cutting edge solutions include : - ASIC Design- Verification- Physical Design- DFT- Circuit Design & Layout- FPGA Design and Emulation

Job Responsibilities<ul><li>Proficient in Verilog, System Verilog, UVM, object-oriented programming,</li><li>Firm understanding of constrained random functional verification, coverage, and assertions.</li><li>Experience with test plan development and development of verification environments from ground up.</li><li>Experience with verification of complex blocks, regressions and coverage closure.</li><li>Experience with gate level simulations and debug.</li><li>Excellent debugging, analytical and problem-solving skills.</li><li>Strong inter-personal, teamwork and communication skills.</li><li>Expected to be highly independent, proactive and result-oriented to achieve verification goals.</li></ul> Preferred Qualifications:<ul><li>Knowledge of I2C, UART, SPI, Ethernet, Video (DisplayPort, CSI/DSI), PCIe and Audio I2S interfaces.</li><li>Experience with lab silicon bring-up, validation and production test support.</li></ul>

&nbsp;Job Description: Responsibilities: Develop and execute verification plans for complex digital RTL. Utilize the latest verification tools and methodologies, including UVM (Universal Verification Methodology), System Verilog, and formal verification techniques. Create and maintain testbenches, test cases, and verification environments. Create and automate regression flow. Perform functional coverage analysis and ensure comprehensive verification coverage. Debug and resolve design and verification issues in collaboration with design engineers. Participate in code reviews and provide feedback to improve design quality. Document verification processes, results, and methodologies. Requirements: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 4 years of experience in digital RTL verification. Proficiency in SystemVerilog, UVM, and other verification methodologies. Experience with industry-standard verification tools such as Cadence, Synopsys, or Mentor Graphics. Strong understanding of digital design principles and RTL coding. Excellent problem-solving and debugging skills.Ability to work effectively in a team environment and communicate clearly with cross-functional teams. Knowledge in I2C/I3C, working with Analog team (developing Analog models), EEPROM interface, Interrupt Controller is a plus Knowledge of scripting languages (e.g., Python, Perl) is a plus. Preferred Qualifications: Experience with formal verification techniques. Knowledge of low-power design and verification techniques

JD: Bachelor's/Master's degree in Electrical Engineering or related field.3 to 15 years of hands-on experience in analog and mixed-signal circuit design, with a focus on high-speed circuits.Proficiency in designing circuits such as Transmitters/Receivers, PLLs, Bias Generators, Band Gap references, and data converters.Strong understanding of analog design fundamentals and IO reliability principles.Experience working with advanced technology nodes (16nm/10nm/12nm/7nm) is highly desirable.Familiarity with scripting languages like Perl, Unix shell, or similar for automation.Excellent written and oral communication skills.Proven experience in mentoring and guiding junior engineers. Interested candidates, Please share me your updated profile to anand.arumugam@modernchipsolutions.com or call me +919900927620

Exp - 4+ yrsLocation - Hyderabad Key Responsibilities: Develop and execute verification plans for analog and mixed-signal integrated circuits, ensuring compliance with design specifications and performance requirements.Design and implement test benches, test cases, and verification methodologies using industry-standard tools and languages.Collaborate with design engineers to identify potential issues and develop solutions to optimize circuit performance and reliability.Conduct simulations, including analog, digital, and mixed-signal simulations, to validate circuit functionality and performance across various operating conditions.Analyze verification results and provide clear and concise feedback to the design team, driving continuous improvement in design methodologies and practices. Requirements: Bachelor's/Master's/Ph.D. degree in Electronics and communications (VLSI)Strong understanding of analog and mixed-signal circuit design principles.Proficiency in verification methodologies and tools such as SystemVerilog, Verilog-A, Verilog-AMS, and Cadence Virtuoso.Experience with simulation tools such as SPICE, AMS simulators, and digital simulators.Excellent problem-solving skills and attention to detail.Effective communication and collaboration skills, with the ability to work in a multidisciplinary team environment. Interested candidates, Please share me your updated profile to anand.arumugam@modernchipsolutions.com

Requirements:• 4+ experience in Analog layouts in advanced nodes (16nm/10nm/7nm/5nm/3nm).• Should have experience on block level, IP level and chip level layouts.• Should have hands on experience in crating layout of critical blocks such as LDO,ADC,DAC,Bandgap,Buck and boost converters etc..• Good understanding of analog layout fundamentals such as matching,WPE,STI,LOD,Electromigration,crosstalk,latchup etc..• Ability to understand design constrains and implement high quality layouts.• Strong debug and problem solving skills for LVS,DRC,Antenna and EM/IR.• Multiple tape out support experience will be an added advantage.• Excellent written and oral communication skills required.• Proven experience in mentoring and guiding junior engineers. Interested candidates, Please share me your updated profile to anand.arumugam@modernchipsolutions.com