Company Overview

Modernize Chip Solutions Pvt. Ltd. is a leading semiconductor services provider offering end-to-end solutions to the global semiconductor industry. Known for our cutting-edge services in ASIC Design, Verification, Physical Design, DFT, Circuit Design & Layout, and FPGA Design and Emulation, we are headquartered in Hyderabad, Telangana, and have a strong team of 200-500 employees.

Job Overview

We are seeking a Mid-Level RTL Design Engineer for a full-time position located in Bangalore or Hyderabad. The candidate must have a minimum of 4 years of relevant industry experience, with expertise in Verilog, SystemVerilog, and ASIC Design being mandatory.

Qualifications and Skills

• Proficiency in Verilog is mandatory as it is essential for designing and verifying digital circuits at the register-transfer level.
• Experience with SystemVerilog (Mandatory skill) for efficient hardware description and verification tasks.
• Strong background in ASIC Design (Mandatory skill) ensuring successful physical implementation of complex integrated circuits.
• Knowledge of VHDL is required for developing alternative approaches to digital logic design.
• Understanding of UVM which is crucial for automated functional verification processes.
• Experience with Synthesis Tools for transforming RTL models into gate-level designs that meet performance and size constraints.
• Competence in using RTL Simulation Tools to verify the functionality of digital designs through simulation models.
• Experience in SoC integration processes, ensuring cohesive interaction of different blocks within the system on chip.
• Proficiency in lint tools to identify potential issues in code quality and design errors.
• Experience with CDC (Clock Domain Crossing) design and verification.

Roles and Responsibilities

• Design and develop RTL code for advanced digital systems, ensuring performance and functional requirements are met.
• Collaborate with cross-functional teams to deliver high-quality semiconductor services aligned with industry standards.
• Conduct thorough verification of designs using SystemVerilog and UVM methodologies.
• Optimize ASIC designs to meet power, performance, and area targets through synthesis and layout stages.
• Maintain comprehensive documentation of design processes and testing outcomes for continuous improvement.
• Participate in design reviews, providing actionable insights for project advancement and risk mitigation.
• Stay updated with emerging trends and technologies in the semiconductor industry to drive innovation and quality.
• Integrate multiple design blocks into a cohesive SoC solution, ensuring seamless operation and performance.