PD methodology and library validation Role:

The individual would work in Design Enablement team for Physical Design flow and library validation.

This includes RTL to GDS2 integration validation of test blocks implemented with different std cell architectures, macros and across different technologies.

Sign-off flow validation like STA, DRC, LVS, PEX will be part of this role.

Skills: Required:

7-12 year experience in following areas:

Good overall understanding of VLSI digital PD methodology Experience with Floorplan, Placement, Routing and Sign-off verification including STA, DRC, LVS.

Understanding of std-cell libraries, EDA views like lib, lef, ndm, timing in the context of Physical design flow.

Technology nodes 22, 16, 5 nm nodes Working knowledge with Synopsys and Cadence PnR tools

Debugging and root cause analysis Desired:

Conceptual understanding of STA, Power/IREM analysis Good communication and team working skills.

Should possess B.Tech/M.Tech in Electronics or allied fields.