Design for Testability - DFT
Design for Testability - DFT
117
Applications
Bengaluru
Full-Time
Senior: 5 to 10 years
Posted on Feb 03 2025
About the Job
Skills
Tessent
DFTMax
Boundary Scan
Scan Chain Insertion
Memory BIST
Logic BIST
JTAG
ATPG
Description:
- Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
- Generate and validate ATPG patterns using simulations.
- Shall Validate the DFT implementation using RTL and Gate level simulation.
- Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
- Must have experience with Siemens, Synopsys and/or Cadence Cad tools.
- Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python
About the company
Modernize chip solutions is one of the fastest-growing semiconductor services company. We deliver end-to-end solutions of the best quality with the shortest development cycle to the global semiconductor industry. Our cutting edge solutions include : - ASIC Design- Verification- Physical Design- DFT- Circuit Design & Layout- FPGA Design and Emulation
Modernize chip solutions is one of the fastest-growing semiconductor services company. We deliver end-to-end solutions of the best quality with the shortest development cycle to the global semiconductor industry. Our cutting edge solutions include : - ASIC Design- Verification- Physical Design- DFT- Circuit Design & Layout- FPGA Design and Emulation
Industry
Semiconductor Manufacturi...
Company Size
51-200 Employees
Headquarter
Hyderabad, Telangana
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