Location- Bangalore.

JD:

Assist MTR verification team with various verification tasks related to memory test & repair system and its components. Run weekly regressions and debug any failures. Generate weekly regression statistics. Help with synthesis, CDC/RDC analysis. Support customers with verification related issues.

Technical :

Logic verification, UVM, system level verification, automation/scripting, coverage analysis, functional coverage, basic perl, synthesis, CDC/RDC analysis.

- Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)

- Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)

- Will need to be hands-on, defining constraints, and margins based on tech nodes, incorporating feedback from the PD Team in the SDC

- Good knowledge of Functional & DFT modes and constraints, Signal integrity, Good knowledge de-rates (OCV, AOCV, POCV)

-Good scripting skills; experience in Tempus is a plus