Key Responsibilities

• Develop detailed micro-architecture specifications and actively participate in technical reviews.
• Design and implement RTL for complex functional blocks, meeting functionality, timing, performance, and power requirements.
• Collaborate on modules such as FIFO, cache, queue managers, schedulers, packet processors, MAC, and more.
• Work closely with verification teams to debug issues and improve functional/code coverage.
• Perform front-end design tasks including linting, CDC analysis, and formal property verification.
• Support synthesis, timing analysis, timing closure, and backend activities like floor planning and ECOs.

Key Skills

• Strong proficiency in RTL design and micro-architecture for networking solutions.
• Solid background in Ethernet switch/router and NIC architecture.
• Hands-on experience with front-end design tools and methodologies.
• Familiarity with scripting languages (e.g., Python, Perl, TCL) for automation is a plus.
• Excellent analytical, debugging, and communication skills.

Preferred Qualifications

• Master’s or PhD in Electrical Engineering, Computer Engineering, or related field.
• Experience with AI accelerators, networking protocols, or SoC integration.