Softnautics is an ISO 27001:2013 certified, Silicon Valley-based semiconductor and embedded AI solutions company with design expertise in systems software, FPGA, and VLSI IP development. With more than a decade of global project execution experience, Softnautics continues to bring digital and product transformation to businesses across the industries. We offer engineering services comprising FPGA design, verification, DevOps, MLOps, multimedia, computer vision, deep learning, edge intelligence, and more. Our portfolio also includes VLSI IP in the fields of USB, Security, and Encryption with Verification IPs (VIP). 
The companyâs service offerings include 

1)	Software services:
â¢	Platform Engineering
â¢	AI Engineering
â¢	Multimedia Engineering
â¢	Digital Engineering
â¢	Network Engineering
â¢	Quality Engineering

2)	VLSI Services
â¢	Design
â¢	Verification &amp; Validation

3)	IP Portfolio	
â¢	USB
â¢	Security
â¢	Encryption
â¢	Reed Solomon Codec
â¢	Erasure Codec

Backed by a proven track record of success, Softnautics has been accelerating customer execution with its headquarter in Santa Clara and development centers in Ahmedabad and Pune. Our diverse talent pool enables us to design optimized, effective, scalable and cost-effective end to end solutions, enabling our customers to rely on us in the competitive market.
With over 10+ years of experience, Softnautics continues to offer technological innovations and rich IP legacy in connectivity, memory, security, and storage. With end-to-end expertise in the specification, architecture, design, verification, validation, system-level bring-up and application testing on various FPGA/ASIC/CPUs/Controllers platforms, we help create future-proof solutions with accelerated time to market.

Corporate Video: https://www.youtube.com/watch?v=tT6PyPDOuF4
To request information, write to business@softnautics.com or visit www.softnautics.com

We are looking for experienced FPGA Design Engineer.As FPGA Design Engineer at Infinera you will work for a high complexity DWDM equipment for long haul network applications. You will work in close collaboration with multi location cross-functional R &amp; D teams. Our work includes everything from product concept to finished product - a process that spans over the entire product development cycle. The team takes full responsibility for delivery on time with the right quality.&nbsp;As an FPGA Design engineer, you will be responsible for writing functional spec, device selection, writing RTL code, synthesis, timing closure, verification support, generating image, bringing up in lab, supporting board and SW team. Candidate should be capable of handling projects independently and strong will to drive for solutions.&nbsp;Education Necessary:&nbsp;Candidates must have a Bachelor’s degree or higher in EE with very good academics.&nbsp;Roles &amp; Responsibilities:·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Must have 5-10 years&nbsp;of experience in developing specs, micro-architecture, RTL designs, verification support, lab bringup, design debug.&nbsp;·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Must have strong RTL coding skill for digital designs. ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Experience with FPGA design tools like Quartus, Vivado, Lattice.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Exposure of verification and debug of RTL designs·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Working knowledge on HW (board or equivalent platform) is preferred. ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Structured and thorough with analytical and troubleshooting skills.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Familiarity with scripting languages such as perl is desired.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Good written and oral communication skills are required.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Flexible, innovative, self-driven and willing to take own initiatives.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Highly motivated team player.

He / She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He / She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.·&nbsp;Provide technical guidance, mentoring to physical design engrs.·&nbsp;Interface with front-end ASIC teams to resolve issues.·&nbsp;Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.·&nbsp;Timing closure on DDR2/DDR3/PCIE interfaces.·&nbsp;Excellent communication skills.·&nbsp;Strong Background of ASIC Physical Design: Floor planning, P&amp;R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.·&nbsp;Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.·&nbsp;Expertise in scripting languages such as PERL, TCL.·&nbsp;Strong Physical Verification skill set.·&nbsp;Static Timing Analysis in Primetime or Primetime-SI.·&nbsp;Good written and oral communication skills. Ability to clearly document plans.·&nbsp;Ability to interface with different teams and prioritize work based on project needs.

Responsibilities·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Understand the standards/specifications ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Architecture development and documenting implementation level details·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands on work for every aspect of verification cycle·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Responsible for the compliance with the latest Methodologies.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Developing Verification IPs·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Define Functional Coverage matrix and Comprehensive Test plan·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Regression management and functional coverage closure·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;DUT integration and verification for IP delivery sign-off·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Leading small team&nbsp;Person SpecificationRequired Skills: ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands-on experience of complete verification cycle with strong verification concepts·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Strong knowledge of Verilog, SystemVerilog and UVM·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Experience in UVM based Verification IP development ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Experience in AMBA AXI/AHB/APB System buses ·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands on work experience on any of PCIe/Eth/USB/DDR etc.·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Hands on experience with System Verilog Assertions·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Scripting for automation, release process, simulations, regressions·&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Good command over written and oral communication&nbsp;Desirable Skills: <ol><li>Lead the Verification IP development with 2 or more junior engineers</li><li>Exposure to full verification cycle</li></ol>&nbsp;&nbsp;