SignOff Semiconductors Pvt Ltd, incorporated in 2015 in Bangalore, with the founders coming from companies like Intel, LSI and Texas Instruments. Signoff is engaged in VLSI services and turn key projects maintaining the core values of "Quality and Commitment". Come and join very Young and Dynamic team to grow your career to the next level.

ROLES &amp; RESPONSIBILITIES<ul><li>Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Clock Tree planning &amp; analysis, Routing ,Timing Budgeting. Signoff STA closure with SI analysis , Derate etc. ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis &amp; fixes, Low Power solution development &amp; implementation</li><li>Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold</li></ul> Job Description: <ol><li>Good exposure in handling block/SOC level RTL-gds2.</li><li>Capable in handling block-level timing closure.</li><li>Excellent knowledge on all low power &amp; signoff checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.</li><li>Good scripting skills (TCL/SHELL/PERL).</li><li>Experience on low power implementation techniques is preferred.</li><li>Prior experience in lower tech nodes like 10nm, 7nm, 5nm is preferred.</li><li>Synopsys/Cadence tool experience is preferred.</li><li>Should be comfortable with Signoff methodologies and guidelines.</li><li>Expertise in Floor Planning, Power Planning, CTS.</li><li>Handling Client requirements and day to day activities</li></ol> <h3>Requirements</h3> Required Qualification: <ol><li>Bachelor’s degree in Electronics &amp; Communication/Electrical &amp; Electronics. Master’s degree in VLSI is preferred.</li><li>Experience 8+&nbsp;years of relevant experience</li><li>Proven ability to identify, assess and solve problems</li><li>Analytical with good interpersonal skills</li><li>Good Communication</li><li>Excellent team player</li><li>High Integrity</li><li>Mentoring Team Members</li><li>Prior experience of leading a team of 5-8 Engineers.</li></ol>