Key Qualification

• 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices

• 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++

• Well versed with FPGA design flow including design entry, synthesis, Implementation, place

and route, timing constraints and timing closure

• In-depth background in HDL development, Verilog coding, integration, synthesis, debug,

simulation, test bench creation

• Experienced with test planning, test bench architecture and assertions

• Constrained random verification experience with System Verilog and UVM

• Coverage driven verification (code/functional/assertion coverage)

• Demonstrated experience working on FPGA design projects, including work with SoC

(ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces.

• Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers,

soldering

• Effectively communicate with cross functional team for bringing up designs

• Good knowledge with high-speed bus protocols including AMBA/AXI3/AXI4 and low speed

protocols including USB / SPI / UART/ IIC and other native protocols

• Experienced with ADC / DAC / EEPROM and other peripheral component