Exp: 10+ Years

Location: Bangalore

Qualifications:

MS or PhD degree in Electronics Engineering or Electrical Engineering.

10+ years of relevant experience in #ASIC RTL Design and or a combination of ASIC and #FPGA RTL.

Prior #Leadership experience is a must.

Responsible for delivering high quality silicon with all aspects of silicon design including RTL design Integration, #synthesis, front-end #timing constraints, LEC, UPF, #lowpower design flows etc.

Must also have a strong understanding of all phases of development in ASIC design including #architecture, micro-architecture RTL design.

Work closely with Product Management and #SoC architecture team to understand product requirements and ensure creation and deployment of highly skilled teams to ensure on-time delivery with high quality for out customers.

Candidate having prior FPGA Design and #Validation #Emulation project experience.

Required hands-on experience with all stages of VLSI Design as well as a proven track record of building and leading interdisciplinary teams in a similar settin.