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Date Posted : 13th Oct 2021
Mid-Level (4 to 6 years)
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Relevant industry experience in the field of DFT for IP or SoC designs Strong in digital logic design, DFT concepts & strong analytical ability Proficient in synthesis with DFT, Scan insertion, ATPG, MBIST(Mandate) & JTAG Expert in design and Implementation of DFT techniques like Boundary Scan, Memory BIST, Scan Insertion & ATPG at a block and top level in advanced technology nodes Hands-on experience with industry Standard tools like Cadence, Synopsys or Mentor Exposure to STA tool, timing closure & ECO implementation for DFT modes is a great plus Prior experience with post-silicon debug is an added advantage. Expertise in scripting languages such as Perl, TCL or shell Strong problem solving & debugging skills Good communication skills