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We're Hiring Pen tab Video Creators ( Video Solution )-work from home to make video solutions for JEE advance, 11,12th ,NEET PCM, and NEETBIO .Educator must have pen tablet and PC or Laptop . Role: Subject Matter Experts Domain : Educational ContentSubjects :▪︎Physics▪︎Maths▪︎Biology▪︎ChemistryLanguage : Hinglish(HINDI+ENGLISH) This is a freelancer job opportunity.Each educator must have pentablet and laptop or PC .

PHYSICAL DESIGN AUTOMATION ENGINEER <h1>Click this link to apply for this position: </h1><a href="https://optimhire.com/developers/jv/106353?ref_code=harshika-govind" rel="noopener noreferrer" target="_blank">https://optimhire.com/developers/jv/106353?ref_code=harshika-govind</a> 4+ years industry experience required <ul><li>Experience with complete Physical Design Flow from RTL to GDS</li><li>Experience with Synthesis &amp; Hierarchical design is a plus</li><li>Experience in taping out in 5nm, 7nm, 16nm multiple technologies</li><li>Expertise in floor planning large blocks or chip</li><li>Experience with Cadence Innovus, Synopsys ICC2, Prime-Time, Calibre</li><li>Scripting experience in Tcl, Perl is must</li><li>Involvement in flow development is a plus</li></ul>

Hiring for Design Verification Engineer <h1>Click below to apply for this position:</h1><a href="https://optimhire.com/developers/jv/106354?ref_code=harshika-govind" rel="noopener noreferrer" target="_blank">https://optimhire.com/developers/jv/106354?ref_code=harshika-govind</a> <ul><li>UVM, SV, C/C++&nbsp;based verification.</li><li>Strong knowledge of SV/ UVM based debugging.</li><li>Experience in constraint randomization based verification.</li><li>Strong knowledge of UVM assertion based verification."</li><li>ARM CPU based verification.</li><li>Should have develop verification bench architecture, Test plan, coverage &amp; assertion plans.</li><li>Gate Level simulation &amp; debugging.</li><li>Should have develop verification bench architecture, Test plan, coverage &amp; assertion plans.</li><li>Candidates having 3+ years to 15 years of Industry Experience is counted</li></ul>

PHYSICAL DESIGN AUTOMATION ENGINEER <h1>Click below to apply for this position: </h1><a href="https://optimhire.com/developers/jv/106353?ref_code=harshika-govind" rel="noopener noreferrer" target="_blank">https://optimhire.com/developers/jv/106353?ref_code=harshika-govind</a> 4+ years industry experience required <ul><li>Experience with complete Physical Design Flow from RTL to GDS</li><li>Experience with Synthesis &amp; Hierarchical design is a plus</li><li>Experience in taping out in 5nm, 7nm, 16nm multiple technologies</li><li>Expertise in floor planning large blocks or chip</li><li>Experience with Cadence Innovus, Synopsys ICC2, Prime-Time, Calibre</li><li>Scripting experience in Tcl, Perl is must</li><li>Involvement in flow development is a plus</li></ul>

<h3>Hiring for the below position:</h3> <h2>Click below to apply now:</h2> <a href="https://optimhire.com/developers/jv/98305?ref_code=harshika-govind" rel="noopener noreferrer" target="_blank">https://optimhire.com/developers/jv/98305?ref_code=harshika-govind</a> Job Title: Design for Test DFT Engineer.5+ years industry experience required <ul><li>Experience with Hierarchical DFT Architecture.</li><li>Experience using Synopsys or Mentor test tools.</li><li>Experience in Scan Insertion, test Muxing, ATPG, MBist &amp; pre/post-layout simulation.</li><li>Expertise in Top Level DFT switching with DFT Architecture experience will add value.</li><li>Expertise in test clock strategy &amp; muxing required .</li><li>Expertise in test timing constraints for shift, capture, mbist or any special mode &amp; timing closure for these modes.</li><li>Familiar with low power testability, state tables, and components (LS, ISO, RET).</li><li>Familiar with JTAG for board level interconnect testing.</li><li>Programming experience in Tcl &amp; Perl is must.</li><li>Involvement in flow development is a plus.</li></ul>

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