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Looking for Design & Verification Engineers

Mid-Level (4 to 6 years)

About the Job


Universal Verification Methodology (UVM)
Asic Verification
System verilog
  • Looking for an IP/SOC design verification engineer. 
  • Must have experience in System Verilog and UVM. 
  • Good to have experience in any protocol like AXI, AMBA, I2C, DDR, PCIe, USB, Ethernet, Multimedia etc.,. 
  • Should have good debugging and analytical skills. 
  • Good to have Scripting knowledge (Python/Perl/shell). 
  • Good communication skills and ability, desire to work as a team player. 

Roles and responsibilities: 

  • Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies. 
  • You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. 
  • Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. 
  • Use advanced verification methodologies like SV/UVM. 

About the company

DIGICOMM Semiconductor Pvt Ltd is a young semiconductor solutions provider.We accentuate Industry's business by providing our skilled and professional, technical services to fasten SOC development life cycles. DigiComm offers a exclusive combination of research and development consultancy, to Semiconductor Vendors. Established in 2012, we are committed to higher end technical assistance to ou ...Show More


Semiconductor Manufacturi...

Company Size

51-200 Employees