Company:MNC (Direct Payroll)

Location :Hyderabad

Experience-4 to 7years

Role:RTL Design Engineer

• Strong in digital design.
• Strong in Xilinx Vivado IP & IPI tools till bit-generation.
• Knowledge of VHDL/Verilog/System Verilog.
• Lint/CDC/Timing Closure
• Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up.

Madatory Skills:

RTL coding, IP design, CDC, LINT, Vivado Testing Modify/update existing IP as per requirements

Vivado/Xilinx tools

VHDA,Verilog

Bachelor’s/Master’s in ECE