Responsibilities:

· Develop testbenches using System Verilog and UVM for functional and power aware RTL verification.

· Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.

· Develop test plan, UVM based test sequences, layered sequences, virtual sequencers.

· Drive closure of verification metrics to cover verification space. Work with team to identify and close gaps in functional, power aware and Gate level timing simulation.

· Develop ‘C’ testcases for HW-FW simulation and FPGA prototyping.

· Regression setup, debug of RTL and gate level netlist.

· Review industry standard spec and augment test plan to improve quality of verification.

· Actively participate in post silicon bring up, validation and compliance testing and debug.

· Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product.

Qualification:

· Proven track record of verification, taking several chips from specification to tape out.

· Proven expertise with UVM and/or System Verilog based verification.

· Excellent understanding of ASIC verification methodologies and proven experience of verification closure.

· Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, Jira.

· Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus.

· Strong written and verbal communication skill and ability to work independently.